Leakage Reduction Techniques for Nanometer Scale CMOS Circuits

As we enter the nanoscale regime, power reduction is of increasing importance, but the established leakage reduction techniques will become less effective. Subthreshold leakage is being joined by band-to-band tunneling and gate leakage as the primary leakage mechanisms. The increased significance of these leakage components threatens the usefulness of some traditional leakage reduction techniques such as stacking and reverse body bias. We present modified versions of these techniques that result in lower total leakage (sub-threshold + gate + band-to-band tunneling) across future technology generations. These modified techniques consider the significance of each leakage mechanism in a given technology generation and make trade-offs accordingly. A novel stacking technique of input vector selection based on the relative contributions of sub-threshold leakage and gate leakage results in up to a 44% reduction in leakage compared to traditional stacking in 50nm devices. An optimal body bias selection technique bas ed on the relative contributions of sub-threshold leakage and band-to-band tunneling results in up to a 42% savings in leakage compared to the zero body bias case for 50nm devices. Since these techniques weigh the relative contributions of leakage components, they reflect the changing requirements as technologies scale.